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CY29658
2.5V or 3.3V 200-MHz 10-Output Zero Delay Buffer
Features
* * * * * * * * * * * * * Output frequency range: 50 MHz to 200 MHz Input frequency range: 50 MHz to 200 MHz 2.5V or 3.3V operation Ten clock outputs: drive up to 20 clock lines One Feedback output LVPECL reference clock input 150-ps max output-output skew Phase-locked loop (PLL) bypass mode Spread AwareTM Output enable/disable Pin-compatible with MPC9658 and MPC958 Industrial temperature range: -40C to +85C 32-Pin 1.0mm TQFP package
Description
The CY29658 is a low-voltage high-performance 200-MHz PLL-based zero delay buffer designed for high-speed clock distribution applications. The CY29658 features an LVPECL reference clock input and provides ten outputs plus one feedback output. VCO output divides by two or four per VCO_SEL setting (see Function Table). Each LVCMOS-compatible output can drive 50 series- or parallel-terminated transmission lines. For series-terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:20. The PLL is ensured stable given that the VCO is configured to run between 200 MHz to 500 MHz. This allows a wide range of output frequencies from 50 MHz to 200 MHz. For normal operation, the external feedback input, FB_IN, is connected to the feedback output, FB_OUT. The internal VCO is running at multiples of the input reference clock set by the feedback divider (see Frequency Table). When PLL_EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply. When BYPASS# is set LOW, PLL and output dividers are bypassed resulting in a 1:11 LVPECL to LVCMOS high performance fanout buffer. For normal PLL operation, both PLL_EN and BYPASS# are set HIGH.
Block Diagram
Pin Configuration
VCO_SEL
FB_OUT
VDDQ
VDD 27
VSS
32
31
30
29
28
26
PECL_C LK PEC L_CLK# FB_IN Phase Detector VC O 200-480M LPF VC _SEL O BYPASS# M E# R/O PLL_EN /2 /2
25
FB_O UT Q (0:8) Q 9
AVDD F B _IN BYPASS# P LL_E N M R /O E# P E C L_C LK P E C L_C LK # A V SS 1 2 3 4 5 6 7 8
VSS
Q0
Q1
C Y 29658
24 23 22 21 20 19 18 17
Q2 VDDQ Q3 VSS Q4 VDDQ Q5 VSS
9
10
11
12
13
14 Q7
15 VDDQ
Q9
Q8
VDDQ
VSS
Cypress Semiconductor Corporation Document #: 38-07478 Rev. **
*
3901 North First Street
*
San Jose, CA 95134
VSS
* 408-943-2600 Revised May 14, 2003
Q6
16
CY29658
Pin Description[1]
Pin 6 7 Name PECL_CLK PECL_CLK# I/O I, PU I, PU O Type LVPECL LVPECL LVCMOS Description LVPECL reference clock input. LVPECL reference clock input. Pull-up to VDD/2. Clock output.
10, 12, 14, Q(9:0) 16, 18, 20, 22, 24, 26, 28 30 2 FB_OUT FB_IN
O I, PU
LVCMOS LVCMOS
Feedback clock output. Connect to FB_IN for normal operation. Feedback clock input. Connect to FB_OUT for normal operation. This input should be at the same voltage rail as input reference clock. See Table 1. Output enable/disable input. See Table 2. PLL enable/disable input. See Table 2. PLL and output divider bypass select input. See Table 2. VCO divider select input. See Table 2. 2.5V or 3.3V power supply for output clocks.[2,3] 2.5V or 3.3V power supply for PLL.[2,3] 2.5V or 3.3V power supply for core and inputs.[2,3] Analog ground. Common ground.
5 4 3 32 11, 15, 19, 23, 31 1 27 8
MR/OE# PLL_EN BYPASS# VCO_SEL VDDQ AVDD VDD AVSS
I, PD I, PU I, PU I, PU Supply Supply Supply Supply Supply
LVCMOS LVCMOS LVCMOS LVCMOS VDD VDD VDD Ground Ground
9, 13, 17, 21, VSS 25, 29 Table 1. Frequency Table Feedback Output Divider /2 /4 Table 2. Function Table Control VCO_SEL PLL_EN BYPASS# Default 1 1 1
VCO Input Clock * 2 Input Clock * 4
Input Frequency Range (AVDD = 3.3V) 100 MHz to 200 MHz 50 MHz to 125 MHz
Input Frequency Range (AVDD = 2.5V) 100 MHz to 200 MHz 50 MHz to 100 MHz
0 VCO / 1
1 VCO / 2
Bypass mode, PLL disabled. The input PLL enabled. The VCO output connects to the clock connects to the output dividers output dividers Bypass mode with PLL and output dividers bypassed. The input clock connects to the outputs. Outputs enabled Selects the output dividers
MR/OE#
0
Outputs disabled (three-state), VCO running at its minimum frequency
Notes: 1. PU = Internal pull-up, PD = Internal pull-down. 2. A 0.1-F bypass capacitor should be placed as close as possible to each positive power pin (<0.2"). If these bypass capacitors are not close to the pins their high-frequency filtering characteristics will be cancelled by the lead inductance of the traces. 3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQ power supply pin.
Document #: 38-07478 Rev. **
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CY29658
Absolute Maximum Conditions
Parameter VDD VDD VIN VOUT VTT LU RPS TS TA TJ OJC OJA ESDH FIT Description DC Supply Voltage DC Operating Voltage DC Input Voltage DC Output Voltage Output termination Voltage Latch Up Immunity Power Supply Ripple Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Failure in Time Manufacturing test Functional Ripple frequency < 100 kHz Non-functional Functional Functional Functional Functional 2000 10 -65 -40 200 150 +150 +85 150 42 105 Functional Relative to VSS Relative to VSS Condition Min. -0.3 2.375 -0.3 -0.3 Max. 5.5 3.465 VDD + 0.3 VDD + 0.3 VDD / 2 Unit V V V V V mA mVp-p C C C C/W C/W V ppm
DC Electrical Specifications (VDD = 2.5V 5%, TA = -40C to +85C)
Parameter VIL VIH VPP VCMR VOL VOH IIL IIH IDDA IDDQ IDD CIN ZOUT Description Input Voltage, Low Input Voltage, High Peak-Peak Input Voltage Common Mode Range[4] Output Voltage, Low[5] Output Voltage, High[5] Input Current, Input Current, Low[6] High[6] Condition LVCMOS LVCMOS LVPECL LVPECL IOL = 15 mA IOH = -15 mA VIL = VSS VIL = VDD AVDD only All VDD pins except AVDD Outputs loaded @ 100 MHz Min. - 1.7 250 1.0 - 1.8 - - - - - - 14 Typ. - - - - - - - - - - 245 4 18 Max. 0.7 VDD + 0.3 1000 VDD - 0.6 0.6 - -100 100 7 4 - - 22 Unit V V mV V V V A A mA mA mA pF
PLL Supply Current Quiescent Supply Current Dynamic Supply Current Input Pin Capacitance Output Impedance
DC Electrical Specifications (VDD = 3.3V 5%, TA = -40C to +85C)
Parameter VIL VIH VPP VCMR VOL VOH Description Input Voltage, Low Input Voltage, High Peak-Peak Input Voltage Common Mode Output Voltage, Range[4] Low[5] LVCMOS LVCMOS LVPECL LVPECL IOL = 24 mA IOL = 12 mA Output Voltage, High[5] IOH = -24 mA Condition Min. - 2.0 250 1.0 - - 2.4 Typ. - - - - - - - Max. 0.8 VDD + 0.3 1000 VDD - 0.6 0.55 0.30 - V Unit V V mV V V
Notes: 4. VCMR (DC) is the crossing point of the differential input signal. Normal operation is obtained when the crossing point is within the VCMR range and the input swing is within the VPP (DC) specification. 5. Driving one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50 series terminated transmission lines. 6. Inputs have pull-up or pull-down resistors that affect the input current.
Document #: 38-07478 Rev. **
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CY29658
DC Electrical Specifications (VDD = 3.3V 5%, TA = -40C to +85C) (continued)
Parameter IIL IIH IDDA IDDQ IDD CIN ZOUT Parameter fVCO fin Description Input Current, Low
[6]
Condition VIL = VSS VIL = VDD AVDD only All VDD pins except AVDD Outputs loaded @ 100 MHz
Min. - - - - - - 12
[7]
Typ. - - - - 330 4 15
Max. -100 100 7 4 - - 18
Unit A A mA mA mA pF
Input Current, High[6] PLL Supply Current Quiescent Supply Current Dynamic Supply Current Input Pin Capacitance Output Impedance
AC Electrical Specifications (VDD = 2.5V 5%, TA = -40C to +85C)
Description VCO Frequency Input Frequency /2 Feedback /4 Feedback Condition
Min. 200 100 50 0 40 500 1.2 100 50 45 0.1 -200 4.1 - - -
Typ. - - - - - - - - - - - - 5.5 - - - 1.9 - 2.2 1.8 - 2.1 - - - -
Max. 400 200 100 200 60 1000 VDD - 0.6 200 100 55 1.0 225 6.9 150 6 6 - - 100 75 150 1
Unit MHz MHz
Bypass mode (BYPASS# = 0) frefDC VPP VCMR fMAX DC tr, tf t() tPD tsk(O) tPLZ, HZ tPZL, ZH BW tJIT(CC) tJIT(PER) tJIT() tLOCK Parameter fVCO fin Input Duty Cycle Peak-Peak Input Voltage Common Mode Range[8] Maximum Output Frequency Output Duty Cycle Output Rise/Fall times Propagation Delay (static phase offset) Propagation Delay (PLL and divider bypass) Output-to-Output Skew Output Disable Time Output Enable Time PLL Closed Loop Bandwidth (-3dB) Cycle-to-Cycle Jitter Period Jitter I/O Phase Jitter Maximum PLL Lock Time
[7]
% mV V MHz % ns ps ns ps ns ns MHz ps ps ps ms
LVPECL LVPECL /2 Output /4 Output 0.6V to 1.8V PCLK to FB_IN, same VDD PCLK to Q0 - Q9 BYPASS# = 0
/2 Feedback /4 Feedback
- - - -
I/O same VDD
- -
AC Electrical Specifications (VDD = 3.3V 5%, TA = -40C to +85C)
Description VCO Frequency Input Frequency /2 Feedback /4 Feedback Condition
Min. 200 100 50 0
Typ. - - - -
Max. 500 200 125 200
Unit MHz MHz
Bypass mode (BYPASS# = 0)
Notes: 7. AC characteristics apply for parallel output termination of 50 to VTT. Parameters are guaranteed by characterization and are not 100% tested. 8. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t().
Document #: 38-07478 Rev. **
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CY29658
AC Electrical Specifications (VDD = 3.3V 5%, TA = -40C to +85C) (continued)[7]
Parameter frefDC VPP VCMR fMAX DC tr , tf t() tPD tsk(O) tPLZ, HZ tPZL, ZH BW tJIT(CC) tJIT(PER) tJIT() tLOCK Description Input Duty Cycle Peak-Peak Input Voltage Common Mode Range[8] Maximum Output Frequency Output Duty Cycle Output Rise/Fall times Propagation Delay (static phase offset) Propagation Delay (PLL and divider bypass) Output-to-Output Skew Output Disable Time Output Enable Time PLL Closed Loop Bandwidth (-3dB) Cycle-to-Cycle Jitter Period Jitter I/O Phase Jitter Maximum PLL Lock Time I/O same VDD /2 Feedback /4 Feedback 0.55V to 2.4V PCLK to FB_IN, same VDD PCLK to Q0 - Q9 BYPASS# = 0 LVPECL LVPECL /2 Output /4 Output Condition Min. 40 500 1.2 100 50 45 0.1 -200 3.6 - - - - - - - - - Typ. - - - - - - - - 4.8 - - - 1.9 - 2.2 1.8 - 2.1 - - - - Max. 60 1000 VDD - 0.9 200 125 55 1.0 225 6.0 150 6 6 - - 100 75 150 1 ps ps ps ms % ns ps ns ps ns ns MHz Unit % mV V MHz
Zo = 50 ohm Differential Pulse Generator Z = 50 ohm Zo = 50 ohm Zo = 50 ohm RT = 50 ohm RT = 50 ohm
VTT
VTT
Figure 1. AC Test Reference for VDD = 3.3V / 2.5V
PECL_CLK PECL_CLK
PECL_CLK
V PP
VCMR
PECL_CLK
V PP
VCMR
VDD
VDD
FB_IN
Qn
t ()
VDD/2 GND
VDD/2
tPD
GND
Figure 2. Propagation Delay t(), Static Phase Offset
Figure 3. Propagation Delay tPD, PLL Bypass
Document #: 38-07478 Rev. **
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CY29658
VDD VDD/2
VDD VDD/2 GND
tP
T0 DC = tP / T0 x 100%
Figure 4. Output Duty Cycle (DC)
GND
VDD VDD/2
tSK(O)
Figure 5. Output-to-Output Skew tsk(O)
GND
Ordering Information
Part Number CY29658AI CY29658AIT 32-pin TQFP 32-pin TQFP - Tape and Reel Package Type Product Flow Industrial, -40C to +85C Industrial, -40C to 85C
Package Drawing and Dimension
32-lead Thin Plastic Quad Flatpack 7 x 7 x 1.0mm A32
51-85063-*B
Spread Aware is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07478 Rev. **
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(c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY29658
Document History Page
Document Title:CY29658 2.5V or 3.3V 200-MHz 10-Output Zero Delay Buffer Document Number: 38-07478 Rev. ** ECN No. 126716 Issue Date 05/19/03 Orig. of Change RGL New Data Sheet Description of Change
Document #: 38-07478 Rev. **
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